# PROMPT — AI + KiCad 10: fabrication-ready PCB from my schematic
# (ESP32-C3 DC Power Meter, Rev B) — attach: Schematic_RevB.pdf

I am an engineer (power electronics). KiCad 10, Windows.
Project folder: <your KiCad project folder>
Goal: professional, fabrication-ready 2-layer PCB, 70 x 50 mm, 1.6 mm,
DRC = 0 errors, 0 warnings, 0 unconnected, plus a full fabrication package.
Sheet 1 = schematic; sheet 2 = parts, KiCad footprints, mounting holes,
layout rules. Do not change the circuit or substitute parts.

================ HOW YOU MUST WORK ================
1. METHOD: you edit my .kicad_pcb / .kicad_pro files directly (plain-text
   S-expressions) with Python in your workspace. Do NOT give me KiCad
   Scripting Console scripts unless I ask (KiCad's Python link goes stale,
   error 'SwigPyObject' has no attribute ..., and wastes hours).
2. Before every file you send me: parse it back, verify it offline
   (overlaps, clearances, pads on track paths, connectivity, balanced
   parentheses), diff it against my original (only intended changes),
   and report PASS/FAIL per check. Never send an unverified file.
3. When something fails: ask for the DRC report or the file, find the
   cause by calculation, change only what is broken. Do not guess or
   rewrite. Say what you verified and what only KiCad/I can verify.
4. Short answers, compact tables. Warn me before anything that uses a lot
   of AI usage and offer a cheaper way.

================ FILE RULES (KiCad 10) ================
- Keep my files' line endings (Windows CRLF) and UTF-8 (µ, Ω present).
- Nets are written by name: (net "IN+"). New items get a new uuid.
  Insert new top-level items before the final (embedded_fonts no).
- Pad position = footprint (at x y a) + pad offset rotated by footprint
  angle a (KiCad: x' = x cos a + y sin a, y' = -x sin a + y cos a; y down).
  Pad angle in the file already includes the footprint angle.
  Flipped (B.Cu) footprints are already mirrored in the file.
- Moving/rotating a footprint: change only its (at ...) line (and the pad
  'at' angles consistently); never edit footprint geometry.
- End tracks at pad centres (pads are roundrect; corners are rounded).
- Tell me every time: close KiCad first, keep a backup copy of my file,
  open with the PCB Editor button, press B, run DRC.

================ KNOWN PITFALLS (all happened before) ================
- Module: ESP32-C3-WROOM-02 (RF_Module:ESP32-C3-WROOM-02) only. NOT the
  bare ESP32-C3 chip, NOT ESP32-C3-DevKitM-1 (dev board), NOT ESP-WROOM-02
  (ESP8266). Its courtyard includes the antenna keep-out: place by the
  module BODY (F.Fab outline), not the courtyard.
- USB-C (Connector_USB:USB_C_Receptacle_HRO_TYPE-C-31-M-12): shield pads
  are "SH". Unused pads: J1 A8/B8; U1 3,4,5,6,11,12 (only if the PDF says NC).
- NET CLASS WIDTH MUST FIT THE FINEST PIN: check track width + 2 x
  clearance against the pin pitch of every part on that net. INA226
  (MSOP-10, 0.5 mm pitch, 0.35 mm pads, 0.15 mm gap) is on IN+, SENSE_P,
  SENSE_N, GND, +3V3, SDA, SCL, ALERT → those classes must be <= 0.20 mm
  track with 0.15 mm clearance. (A 0.40 mm IN+ class made Freerouting skip
  U2 pad 8.) 10 A is carried by copper zones, not by class tracks.
- Screw terminals J2/J4 (Phoenix MKDS 5.08 horizontal): wire entries must
  face OUT over the right board edge, body on the board. Their courtyard is
  almost symmetric, so do NOT decide direction from the courtyard: use the
  F.Fab/F.SilkS front marks (pin-1 triangle side = wire entry side) and ask
  me to confirm in 3D. Never rotate them after copper (swaps IN+ and GND).
- R5/R6: pad 1 faces the shunt; RS1 pad 1 (IN+) faces J2. Check that no
  other pad lies on any Kelvin track path before writing it.
- Decoupling cap next to the module 3V3 pin may go on the bottom side if
  courtyards clash; part references may go to the Fab layer for a clean
  silkscreen (0 silk warnings).

================ DESIGN TARGETS ================
Rules: min track 0.15, clearance 0.15, min drill 0.20 (via 0.6/0.3),
copper-to-edge 0.30 mm. Net classes: IN+/OUT+ 0.20 mm (clearance 0.15,
zones 0.30); +5V 0.50; +3V3 0.40 only where no MSOP pin, else 0.20;
SENSE_P/N 0.25 if it fits the MSOP pin, else 0.20; USB_DP/DN 0.25 with
diff-pair width >= 0.25 (KiCad's 0.125 default fails DRC). Verify each
against pin pitch before writing.
Placement: H1–H4 M3 at 3.5 mm from corners; J1 USB-C on the left edge,
U4 ESD right behind it, in line with module pads 13/14 (USB); U1 antenna
at the bottom edge, keep-out copper-free on both layers; C3/C4 at module
pad 1; EN/BOOT parts (R3, C5, R11, R4) beside the module; SW1/SW2 along
the top edge; LDO U3 + C1/C2 top-left; J3 OLED header top (OLED module
must not cover the LED D1); J2 (IN) → RS1 → J4 (OUT) straight on the right
edge; INA226 U2 next to RS1 with R5/R6/C7 between; D2 TVS inside the IN+
area beside RS1.
Copper: IN+ and OUT+ zones on F.Cu (each covers only the outer half of its
shunt pad; inner half is the Kelvin tap; width >= 4.7 mm for 10 A,
IPC-2221 1 oz outer, 20 °C rise); solid zone connection on J2-2/J4-2; GND
pour on B.Cu (thermal reliefs elsewhere); Kelvin tracks 0.25 mm from the
inner half of RS1 pads to R5/R6 pad 1; one GND via per SMD GND pad
(fan-out) so the autorouter cannot fence a GND pad off; bottom silkscreen
"<your name>", "<project name>", "Rev B" (+ <your website or channel>
if it fits cleanly).

================ WORKFLOW AND MY GATES ================
Step 1  Parts table from the PDF: ref, value, KiCad symbol, footprint,
        pin-1 pad, special pads. → WAIT for my OK.
Step 2  Write ESP32C3_DC_Power_Meter.net (exact refs, values, footprints,
        net names, pin numbers from the PDF; NC pins get no net; H1–H4 no
        net). Self-check: every pin in the PDF appears once, no net with a
        single pin unless the PDF says so. → I import it into an empty
        board (link by reference), save, and send you .kicad_pcb + .kicad_pro.
Step 3  You write outline, rules and net classes (.kicad_pro) and the
        placement (.kicad_pcb). Report: all parts inside the outline, no
        courtyard overlaps, terminals/USB/antenna checks, distances
        (C4–U1 pad 1, U2–RS1, C6–U2). → I check in 3D. WAIT for my OK.
Step 4  You write zones, Kelvin tracks, GND fan-out vias, bottom silk.
        Report width of each power zone, pads-on-path = none.
        → I run Freerouting, save, run DRC, send you DRC.rpt + .kicad_pcb.
Step 5  You fix leftovers in the routed file (single tracks with clearance
        check, widths, dangling vias, GND islands) until DRC is 0/0/0.
Step 6  Professional pre-fab checklist for me to tick (DRC 0/0/0; 10 A path
        width; Kelvin at shunt pads; antenna keep-out; GND pour stitched;
        no slivers/acid traps; silk off pads and readable; polarity/pin-1
        marks for LED, TVS, USB, OLED; holes clear; outline closed; 3D).
Step 7  Fabrication package steps for KiCad 10: Gerbers (F/B Cu, Mask,
        Silk, Paste, Edge.Cuts), Excellon drill + map, BOM, position file,
        fab notes (2 layers FR-4 1.6 mm, 1 oz, HASL/ENIG, 0.15/0.15 mm,
        0.2 mm drill — confirm with the fab; local fabs may need 0.3 mm
        drill). How to check Gerbers in KiCad's Gerber Viewer before ordering.

Start with Step 1 only.